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Staff ASIC Design Engineer

Careerbuilder US

This is a Contract position in Irvine, CA posted September 18, 2020.

This position requires in-depth experience in these areas: SoC, embedded CPU and bus architectures, networking and control interfaces Communications/DSP and packet processing algorithms, and efficient implementations.

Digital IC design, design for low power and high speed, design for test (DFT) System modeling, RTL coding, Lint/CDC checking, simulation, synthesis, power analysis, timing analysis in Cadence/Synopsys design environments Verilog/System Verilog, C, and scripting languages FPGA/HW emulation and system validation Chip bring up, lab debug and silicon performance validation Self-motivated, excellent communication skills and ability to excel in a team environment MS in EE or Ph.D.

in EE1 Job Requirements: This position requires in-depth experience in these areas: SoC, embedded CPU and bus architectures, networking and control interfaces Communications/DSP and packet processing algorithms, and efficient implementations.

Digital IC design, design for low power and high speed, design for test (DFT) System modeling, RTL coding, Lint/CDC checking, simulation, synthesis, power analysis, timing analysis in Cadence/Synopsys design environments Verilog/System Verilog, C, and scripting languages FPGA/HW emulation and system validation Chip bring up, lab debug and silicon performance validation Self-motivated, excellent communication skills and ability to excel in a team environment MS in EE or Ph.D.

in EE1

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